PUBLISHED PAPERS
2019 |
A New Synchronous-Asynchronous Mixed Pipeline Architecture with Clock-Gating Proceedings Article Duarte L. Oliveira; Nicolly N. M. Cardoso; Gracieth C. Batista; Diego A. Silva; Leonardo Romano Resumo | Links | BibTeX | Tags: Adaptative to Latency, elastic circuits, não disponível, STG specificaition @inproceedings{between2019n\~{a}ob,Digital systems design are usually synthesized in the synchronous paradigm using the global clock signal and they can be implemented in Field Programmable Gate Array (FPGA) and Very Large Scale Integration (VLSI) using Deep-Sub- Micron CMOS (DSM_CMOS) technology. These digital designs implemented in DSM_CMOS technology have the global clock signal as an obstacle which makes it difficult to comply with requirements, such as: performance, power consumption, reusability, etc.; because the wires have significant delays (latency). One solution is to synthesize modules that are insensitive to wires delays, that is, the module adapts to the latency of communication between the modules. In this paper, we propose a new pipeline architecture that is insensitive to latency because it has the property of elasticity, obtained by the pipeline asynchronous communication. Our pipeline can receive data at a frequency unrelated to the global clock signal. Through a case study, a Finite Impulse Response (FIR) filter of order five was used in reason to prove the efficiency of our proposal. Compared to a conventional synchronous pipeline, we achieved a throughput increase of up to 14.7% on Altera's FPGA platform. Keyword Elastic Circuits, STG specification, Adaptive to Latency. |