@inproceedings{Lester2010VHDLb,
title = {Single Clock Control Logic Block (CLB) design for a QWIP-FPA ROIC},
author = {Lester Abreu Faria and F\'{a}bio Durante Pereira Alves and Newton Gomes and Wellington Melo},
url = {https://www.sige.ita.br/edicoes-anteriores/2010/st/VII_3.pdf},
year = {2010},
date = {2010-01-01},
booktitle = {Simp\'{o}sio de Aplica\c{c}\~{o}es Operacionais em \'{A}reas de Defesa 2010 (SIGE2010)},
abstract = {A Control Logic Block (CLB) of a Readout Integrated Circuit for a Quantum-Well Infrared Photodetector Focal Plane Array (QWIP-FPA ROIC) is designed and simulated. Through the use of a single input signal (CLOCK), it can be generated up to twelve synchronized control signals for the management of all QWIP-FPA functions and its interface with indicate better performance than the available devices, which use up to seven external CLOCKS that must be synchronized, inserting extra difficulties in the project. Through an easy implemented topology, designed in VHDL, it is possible to control a 64 cells FPA prototype (8X8 Matrix). Few modifications are required to use this circuit with bigger FPAs.},
keywords = {control logic block, digital design, VHDL},
pubstate = {published},
tppubtype = {inproceedings}
}
A Control Logic Block (CLB) of a Readout Integrated Circuit for a Quantum-Well Infrared Photodetector Focal Plane Array (QWIP-FPA ROIC) is designed and simulated. Through the use of a single input signal (CLOCK), it can be generated up to twelve synchronized control signals for the management of all QWIP-FPA functions and its interface with indicate better performance than the available devices, which use up to seven external CLOCKS that must be synchronized, inserting extra difficulties in the project. Through an easy implemented topology, designed in VHDL, it is possible to control a 64 cells FPA prototype (8X8 Matrix). Few modifications are required to use this circuit with bigger FPAs.
