TRABALHOS PUBLICADOS
2017 |
A Design Tools Flow and New Architecture for Low-Power Gated-clock Synchronous Controllers Proceedings Article Oliveira, Duarte L; Curtinhas, Tiago; Faria, Lester A; Romano, Leonardo @inproceedings{Duarte2017modelsb,Controllers based on Synchronous Finite State Machines (SFSM) are widely used in the design of Embedded in Field Digital Systems (EDS) and can be Programmable Gate Arrays (FPGAs) or VLSI (Very Large Scale Integration). A class little known and very interesting of SFSM in the FPGA or VLSI platforms is the SFSMs of direct output (SFSM_DO). These state machines use the output signals as state signals, thus allowing several advantages when compared to conventional SFSM classes. Of these advantages, we can mention: elimination of glitches in the output signals; reduction of the number of state variables; reduction in latency time. An important requirement in EDS is power consumption. The literature shows that SFSMs with gated-clock have a substantial average reduction in dynamic power. This paper proposes architecture for SFSMs_DO with gated-clock. Through the case study the proposed architecture showed a reduction in the dynamic power of 86.3% when compared with conventional gated-clock SFSMs. |