@inproceedings{Data2020SCAsb,
title = {Design of DES Encryption Algorithm as Bundled-},
author = {Data Asynchronous Pipeline FPGA},
url = {https://www.sige.ita.br/edicoes-anteriores/2020/st/ST_08_2.pdf},
year = {2020},
date = {2020-01-01},
booktitle = {Simp\'{o}sio de Aplica\c{c}\~{o}es Operacionais em \'{A}reas de Defesa 2020 (SIGE2020)},
abstract = {Currently, digital systems that are able to meet major security restrictions are increasingly being demanded, both in the military and in commercial areas. Data security can important be achieved by cryptographic algorithms. An encryption algorithm known as DES (Digital Encryption Standard) was implemented in Field Programmable Gate Array (FPGA) in different synchronous architectures. In this paper we propose an implementation of the DES algorithm in FPGA, in the asynchronous pipeline the implementation in FPGA of two different project styles the proposal asynchronous obtained an average increase of 14.9% in throughput and an average reduction of 66.3% in latency time. Keywords SCAs, pipeline, data-path, SoC, DPA.},
keywords = {data-path, DPA, pipeline, SCAs, SoC},
pubstate = {published},
tppubtype = {inproceedings}
}
Currently, digital systems that are able to meet major security restrictions are increasingly being demanded, both in the military and in commercial areas. Data security can important be achieved by cryptographic algorithms. An encryption algorithm known as DES (Digital Encryption Standard) was implemented in Field Programmable Gate Array (FPGA) in different synchronous architectures. In this paper we propose an implementation of the DES algorithm in FPGA, in the asynchronous pipeline the implementation in FPGA of two different project styles the proposal asynchronous obtained an average increase of 14.9% in throughput and an average reduction of 66.3% in latency time. Keywords SCAs, pipeline, data-path, SoC, DPA.
